1. Field of the Invention
The invention relates to a structure and a method for constructing a double-gate transistor device, particularly a double-gate transistor.
2. Description of the Related Art
Double-gate transistors have a number of different uses. However, construction of vertical double-gate devices has always been somewhat difficult, given alignment problems between the two gates used in the device.
FIG. 1 shows a cross-sectional view of a double-gate device formed on a silicon substrate 10 having a top gate 12 and a bottom gate 14 formed in a buried oxide layer 16. Construction of gates 12 and 14 in this stacked type of device leads to alignment problems between the vertically separated top and bottom gates 12 and 14, respectively. In addition, care must be taken to provide ample connectivity for gate 14.
Simplification and self-alignment in semiconductor processing methods is constantly advantageous. Hence a method which provides a simplified method for forming a double-gate device would be advantageous.
The invention, roughly described, comprises a self-aligned double gate transistor. The transistor includes a first silicon portion on an isolation layer, the silicon portion having formed therein a source region and a drain region separated by a channel region, and having a first side and a second side, the first side and the second side having a first gate oxide and a second gate oxide, respectively, formed thereon; a first silicon gate abutting said first side of said channel region on said insulator; and a second silicon gate abutting said second side of said channel on said insulator.
In a further embodiment, the invention comprises a method for manufacturing a double gate transistor device. The method for manufacturing includes the steps of: providing a substrate having a buried oxide region; depositing a first nitride mask layer having a pattern overlying a silicon region; forming a trench in said substrate with a depth to said buried oxide; forming a gate oxide in said trench; depositing polysilicon in said trench; depositing a second nitride mask layer having a pattern formed perpendicular to said first nitride mask; etching the portion of said polysilicon not underlying said first or second nitride layers; removing said second nitride layer; and implanting an impurity into exposed portions of polysilicon in said trench and of said silicon-on-insulator substrate underlying said second nitride layer.